The present invention pertains to the field of integrated circuits. More particularly, the present invention pertains to efficient address generation for a segmented linear address space.
Integrated circuits typically have address generating circuits for generating the addresses of code or data to be accessed from storage. Processors are an example of an integrated circuit requiring repeated address generation for the retrieval of data or code from storage. The amount of code or data that the processor can access is limited by the size of the linear address space. The size of the linear address space is a function of the width in bits of the address registers in the processor. For example, in a processor having 32 bit registers, the processor can address 232 bytes (or locations). The linear address space of a processor can be divided into segments. Segments can be used to hold the code, data, and a stack for a program or to hold system data structures. If more than one program is running on a processor, each program can be assigned its own set of segments. The processor then enforces the boundaries between these segments and ensures that one program does not interfere with the execution of another program by writing into the other program=s segments. The size of a segment is also known as the size of the effective address space of the processor. Many popular processors have effective address spaces and segments that are 64 kilobytes in size. However, other sizes are possible.
Processors have an instruction pointer containing an instruction address pointing to an instruction in a segment containing code to be executed by the processor. The instruction address indicates the location of the instruction in the linear address space. The instruction address is typically translated into a physical address that is used to retrieve an instruction from a particular location in physical memory or other storage device.
While executing code in a segment, a processor typically increments the contents of the instruction pointer so that the instruction pointer points to the next instruction to be retrieved. However, when the processor encounters a relative branch instruction the contents of the instruction pointer after execution of the relative branch instruction will depend upon the displacement specified in the branch instruction. When the relative branch instruction is executed, a target address is generated using the displacement. The target address is the address of the next instruction to be retrieved by the processor. Upon completion of the execution of the relative branch instruction, the target address is placed into the instruction pointer. For the case where the processor is restricted to the address space of the segment, the target address cannot point to a location outside the code segment. Consequently, after execution of the relative branch instruction the instruction pointer must point to a location between the segment base and the segment base plus the size of the effective address space. For an effective address space of 64 kilobytes, the instruction pointer must point to a location between the segment base (lower boundary) and the segment base plus FFFFH (upper boundary).
Typically, to determine the target address in the linear address space (linear space target address) a processor will first determine the effective space target address. To determine the effective space target address, the segment base is subtracted from the instruction address to produce the effective instruction address. The displacement is added to the effective instruction address to produce the effective space target address. Any carry that results from the sum of the displacement and the effective instruction address is ignored. Irrespective of the value of the displacement, the effective space target address will be between 0000H and FFFFH because the carry is ignored. After determining the effective space target address, the processor will translate the effective space target address to the linear address space by adding the segment base to the effective space target address, thereby generating the linear space target address. Determining the target address in the effective space and translating the effective space target address to the linear address space is computationally intensive and typically requires several clock cycles.
The performance of a processor can be significantly affected by the number of clock cycles required for generating target addresses for relative branch instructions. Since address generation for relative branch instructions is performed frequently, it would be advantageous to decrease the number of cycles.
According to an embodiment of the invention a method of linear space target address generation is described. The method includes generating a selection signal, and generating a linear space target address using the selection signal by generating a plurality of corrected target addresses and selecting the linear space target address from the plurality of corrected target addresses using the selection signal.